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Power Electronics Europe Events
 
IEDM 2019
November 13, 2019 - December 20, 2019

Innovative Devices for an Era of Connected Intelligence – this is the theme of the 2019 IEEE International Electron Devices Meeting (San Francisco, December 7-11, 2019), to reflect the conference’s focus on the processors, memories, 3D architectures, power devices, quantum computing concepts and other technologies needed to drive diverse new applications of electronics technology forward.

The number of papers submitted to the IEDM conference this year is the highest in recent years, no  doubt driven by the fact that new, fast-growing applications for semiconductors require different types of devices,” said Rihito Kuroda, IEDM 2019 Publicity Chair and Associate Professor at Tohoku University. “As a result, several important trends are apparent from this year’s technical program. One is the increasing interest in using 3D techniques to achieve higher levels of integration. Another is the number of papers describing complete technology platforms in wide-ranging areas, from mainstream CMOS scaling to silicon photonics, GaN power devices and human-machine interfaces.” “We see that 3D monolithic integration is really coming on strong, because there are so many different reasons and ways to do it to meet the needs of diverse applications,” said Dina Triyoso, IEDM 2019 Publicity Vice Chair and Technologist at TEL Technology Center America. “Another development which is very apparent is the trend toward design/technology co-optimization, a sign of unprecedented interdisciplinary collaboration between the people who design today’s complex devices and the people who design the manufacturing processes to build them.”

The 65th annual IEDM will feature a technical program of 238 papers given by many of the world’s top scientists and engineers. It will be preceded by a series of 90-minute tutorials and by day-long short courses.

Progress in Si IGBT technology as an ongoing competition with WBG

The Insulated Gate Bipolar Transistor (IGBT) as a high voltage power switch is a combination of a Silicon (Si) power MOSFET and a bipolar transistor. It serves since 30 years as a key component in nearly all medium to high power electronic systems like in industrial drives, UPS, renewables, electric cars and traction. “Tremendous progress in increased power density could be achieved by stepwise reduced on-state and switching losses, increased current densities and maximum junction temperatures. As the wide band gap successor candidates GaN and SiC catching up in the power semiconductor market, it is worth looking closer on today’s Silicon IGBT concepts and asking what future options in IGBT technology are possible in competition to the WBG solutions,” will underline Thomas Laska from Infineon Technologies (www.infineon.com).

The combination of new interconnect solutions together with innovations in cell and vertical structure as well as gate driving concepts shall open the path to much higher power density than today. As a scenario at least two more IGBT generations with overall about 50 % higher power density at reasonable costs may become possible.

Advancements in GaN

A “1200 V Multi-Channel Power Devices with 2.8 Ω⋅mm ON-Resistance,” will be presented by J. Ma from EPFL/Enkris Semiconductor (www.enkris.cn). Lateral GaN-on-Si devices are promising for advanced power ICs because they combine high device performance, low cost, and can make physically smaller systems possible. While GaN HEMTs are commercially available, there is still plenty of room to improve their performance up to the full potential of GaN, and further advances require a major advance in on-resistance while still maintaining high breakdown voltage.

A team led by Swiss EPFL (www.epfl.ch) will report on novel lateral multi-channel AlGaN/GaN power devices with high breakdown voltage (1230 V) and low on-resistance (2.8 Ω⋅mm), resulting in an excellent figure-of-merit of 3.2 GW/cm². The researchers call these devices MOSHEMTs, and they have a multi-channel FinFET-like architecture with slanted tri-gates whose structure can be modified to “tune” device performance. The on-resistance is some 5x lower than previously seen at this breakdown voltage with single-channel devices. Until now it has proven difficult to control multiple parallel channels with a typical gate architecture, but the tri-gate structure has proven to be effective in doing so, and it lends itself to building normally-off – and thus more fail-safe – devices.

A team led by Belgium Imec (www.imec.be) will discuss monolithically integrated GaN-on-SOI ICs for power conversion, which they used to build a complete buck converter that demonstrated 200 V on-chip power conversion at 1 MHz. An SOI (silicon-on-insulator) substrate was used because it eliminates the back-gating effect which wastes power. It also suppresses parasitics, provides effective electrical isolation and reduces the area required. The team comprehensively investigated the technology from multiple vantage points: substrate, buffer, isolation, device, co-integration and circuit. Different components were successfully integrated monolithically, including a HEMT, Schottky barrier diode, MIM capacitor, 2DEG resistor, and resistor-transistor logic.

The Kavli Institute at Cornell University, Ithaca, USA (www.cornell.edu) and Intel Corporation, Components Research (Hillsboro, USA) will introduce “GaN/AlN Schottky-gate p-channel HFETs with InGaN Contacts and 100 mA/mm On-Current”. High-performance wide-bandgap p-channel devices which can be monolithically integrated with established wide-bandgap n-channel devices are broadly desirable to expand the design topologies available in power/RF electronics. This work advances the GaN-on-AlN platform as the most promising p-channel contender to enable wide-bandgap complementary electronics. Toward that end, a new generation of GaN-on-AlN p-channel HFETs is fabricated with on-currents exceeding 100 mA/mm at room temperature under moderate drain bias. This work has demonstrated the strongest on-current performance of any significantly modulating p-channel transistor in the III-Nitrides, encouraging further study of the GaN/AlN platform to power a wide-bandgap CMOS technology.

A “First Demonstration of a Self-Aligned GaN p-FET” by MIT (www.mit.edu), Enkris Semiconductor and Intel will demonstrate a self-aligned p-FET with a GaN/Al0.2Ga0.8N (20 nm)/GaN heterostructure grown by metal-organic-chemical vapor deposition (MOCVD) on Si substrate. The 100 nm channel length device with recess depth of 70 nm exhibits a record on-resistance of 400 Ω·mm and on-current over 5 mA/mm with ON-OFF ratio of 6×105 when compared with other p-FET demonstrations based on GaN/AlGaN heterostructure. The device shows E-mode operation with a threshold voltage of −1 V, making it a promising candidate for GaN-based complementary circuit that can be integrated on a Silicon platform. A monolithically integrated n-channel transistor with p-GaN gate is also demonstrated. The potential of the reported p-FET for complementary logic application is evaluated through industry-standard compact modeling and inverter circuit simulation.

Advancements in SiC

Mitsubishi Electric (www.mitsubishielectric.com) and the University of Tokyo will demonstrate a Si-face 4H-SiC MOSFET with oxygen (O) doping in the channel region for the first time. Compared with a conventional device, the O-doped channel was found to provide lower channel resistance and higher threshold voltage, which is expected from the fact that O acts as a deep level donor in 4H-SiC. By applying this novel technique to vertical 4H-SiC MOSFETs, a 32 % reduction of specific on-resistance (Ron) at a high Vth of 4.5 V is achieved. In order to evaluate gate oxide reliability, negative bias temperature instability (NBTI) of Vth is investigated. The O-doped channel shows a smaller Vth shift, and its acceleration coefficient of the time to Vth shift is similar to that of a conventional one. Therefore, the O-doped channel is found to be a promising approach to further improve NBTI of 4H-SiC MOSFETs by channel engineering using deep level donors.

The “Physical Modeling of Bias Temperature Instabilities in SiC MOSFETs” is the title of the paper given by the TU Vienna (www.iue.tuwien.ac.at) to characterize and simulate charge trapping in lateral SiC MOSFETs. Advanced measurements (eMSM, pMSM, RVS) with long stress and recovery times are conducted on both SiC technologies and fully reproduced through simulations. Simulations rely on the two-state NMP model to describe the charge transitions of the involved border traps. Two electron (shallow and fast) and hole trap bands are identified and used to explain PBTI and NBTI in lateral devices. The shallow traps modeled with similar parameters as in Si/SiO2 suggest an intrinsic charge trapping behavior of SiO2, which is supported by a comparison with slow Vth drifts in vertical devices. Based on the simulations accurate lifetime predictions can be made. While empirical models appear to provide too pessimistic (power law) predictions, the results provide a physics-based extrapolation at operating conditions.

High energy-density thin-film battery

There has been great progress in miniaturizing electronics but the miniaturization of power sources hasn’t kept pace. Although integrated electrochemical capacitors offer high power density, high frequency response and novel form factors, their low energy densities are of limited value for MEMS and autonomous device applications that require long periods between charging. CEA-Leti (www.leti-cea.fr) researchers will discuss a thin-film battery (TFB) with the highest areal energy density yet reported (890 µAh/cm-2) and high power density (450 µAh/cm-2). Built on Silicon wafers using UV photolithography and etching for the successive deposition and patterning of each layer, the thin-film battery integrates a 20 µm thick LiCoO2 cathode in a Li-free anode configuration. It showed good cycling behavior over 100 cycles, and the fact it was built using a wafer-level process opens up the possibility to tightly integrate this battery technology with future electronic devices. AS

www.ieee-iedm.org

 

 

 
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