Features
Power_electronics Features

94% efficient offline flyback switcher IC family - issue 5/2017
Power Integrations announced its Innoswitch3 family of offline CV/CC flyback switcher ICs. The new devices achieve up to 94% efficiency across line and load conditions...
More details...
Linear voltage regulators operate at automotive temperatures
Designed for high reliability, high temperature applications, the CMT-Antares is Cissoid's latest regulator.
More details...
Power Electronics Europe News
 
PolarFire FPGAs interoperate with RF transceiver to lower power
To meet the needs of the wireless communications, medical and defence markets, via a JESD204B interface, the AD9371 wideband RF transceiver offers dual channel transmitters and receivers, integrated synthesisers and digital signal processing (DSP) functions. It can use the cost-optimised, low power, mid-range PolarFire FPGAs to interface and interoperate with JESD204B, while using lower power implementation than competing devices, claims the company.

 

The FPGAs are believed to be the first non-volatile FPGAs providing more power and cost savings in comparison to SRAM FPGAs with 10G transceivers, advanced input/output (I/O), high security and DSP capabilities. They have a 12.7Gbit/s transceiver delivering less than 90mW at 10Gbit/s. Its IP cores, which implement the transmitter and receiver interfaces of the JESD204B standard, can be integrated with JESD204B-based data converters. They support link widths from one to eight, and link rates from 250Mbit/s to 12.5Gbit/s per lane using subclass 0, 1 and 2.

 

The FPGAs and the RF transceiver can be used in wireless communications, defence and industrial markets. Typical uses include high bandwidth applications such as remote radio head (RRH) and active antennae, test and measurement equipment, software defined radios, large multiple input, multiple output (MIMO) and small cells.

 

There is a reference design for customers to run the JESD204B interface on its PolarFire Evaluation Kit using the JESD204B standalone demonstration graphical user interface (GUI) application. The reference design uses the FPGA’s high-speed transceiver blocks, and the CoreJESD204BTX and CoreJESD204BRX IP cores. The reference design and GUI application are available for Microsemi’s Libero SoC PolarFire Design Suite. All customers with a Libero gold (included with kit) or platinum license can access the JESD204B IP cores for no additional fee. 

 

 

 



View PDF
 
Go Back   
Newsletter sign up

Sponsors