Power_electronics Features

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Power Electronics Europe News
AOS refines package for optimal resistance and inductance
The DFN 5.-0 x 6.0mm package is combined with the company’s 40V Shield-Gate Technology (AlphaSGT). The flip-chip package offers a low package resistance and inductance, says the company.


The AOE66410 is suitable for telecommunications applications for secondary rectification (SR), in half bridge configuration for brushless direct current (BLDC) motor applications and battery management where paralleling is important.


The AOE66410 has the same form factor of a standard DFN 5.0 x 6.0mm package but the pad has the largest connection to the PCB, explains the company. This will enable power supply designers to parallel devices more easily and have a larger thermal area to dissipate any losses.


The AOE66410 has a 1mΩ maximum at 10Vgs with a maximum drain current of 100A at 25°C case temperature.


The AOE66410 is immediately available in production quantities with a lead time of 12 to 14 weeks.



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